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4 Mbit (x8) Small-Sector Flash
SST29SF040 / SST29VF040
SST29SF/VF0404Mb (x8) Byte-Program, Small-Sector flash memories
Data Sheet
FEATURES:
* Organized as 512K x8 * Single Voltage Read and Write Operations - 4.5-5.5V-only for SST29SF040 - 2.7-3.6V for SST29VF040 * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 5 MHz) - Active Current: 10 mA (typical) - Standby Current: 30 A (typical) for SST29SF040 1 A (typical) for SST29VF040 * Sector-Erase Capability - Uniform 128 Byte sectors * Fast Read Access Time: - 55 ns for SST29SF040 - 55 ns and 70 ns for SST29VF040 * Latched Address and Data * Fast Erase and Byte-Program: - Sector-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Chip Rewrite Time: 8 seconds (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * TTL I/O Compatibility for SST29SF040 * CMOS I/O Compatibility for SST29VF040 * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST29SF040 and SST29VF040 are 512K x8 CMOS Small-Sector Flash (SSF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29SF040 devices write (Program or Erase) with a 4.5-5.5V power supply. The SST29VF040 devices write (Program or Erase) with a 2.73.6V power supply. These devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST29SF040 and SST29VF040 devices provide a maximum Byte-Program time of 20 sec. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of at least 10,000 cycles. Data retention is rated at greater than 100 years. The SST29SF040 and SST29VF040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the
(c)2004 Silicon Storage Technology, Inc. S71160-10-000 2/04 1
SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST29SF040 and SST29VF040 devices are offered in 32lead PLCC and 32-lead TSOP packages. See Figures 1 and 2 for pin assignments.
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
Read
The Read operation of the SST29SF040 and SST29VF040 devices are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3).
Chip-Erase Operation
The SST29SF040 and SST29VF040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1s" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 18 for the flowchart. Any commands written during the ChipErase operation will be ignored.
Byte-Program Operation
The SST29SF040 and SST29VF040 devices are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 s. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.
Write Operation Status Detection
The SST29SF040 and SST29VF040 devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The SST29SF040 and SST29VF040 offer Sector-Erase mode. The sector architecture is based on uniform sector size of 128 Bytes. The Sector-Erase operation is initiated by executing a six-bytecommand sequence with Sector-Erase command (20H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (20H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figure 8 for timing waveforms. Any commands issued during the Sector-Erase operation are ignored.
(c)2004 Silicon Storage Technology, Inc.
S71160-10-000
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2
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
Data# Polling (DQ7)
When the SST29SF040 and SST29VF040 devices are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 16 for a flowchart.
Software Data Protection (SDP)
The SST29SF040 and SST29VF040 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of threebyte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of a six-byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC.
Product Identification
The Product Identification mode identifies the devices as SST29SF040 or SST29VF040 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 10 for the Software ID Entry and Read timing diagram and Figure 17 for the Software ID Entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST29SF040 SST29VF040 0000H 0001H 0001H Data BFH 13H 14H
T1.2 1160
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 16 for a flowchart.
Data Protection
The SST29SF040 and SST29VF040 devices provide both hardware and software features to protect nonvolatile data from inadvertent writes.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 11 for timing waveform, and Figure 17 for a flowchart.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V for SST29SF040. The Write operation is inhibited when VDD is less than 1.5V. for SST29VF040. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
(c)2004 Silicon Storage Technology, Inc.
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3
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffers & Latches Y-Decoder CE# OE# WE# DQ7 - DQ0
1160 B1.0
Control Logic
I/O Buffers and Data Latches
WE#
VDD
A12
A15
A16
A18
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
5 6 7 8 9 10 11 12 13
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
A17
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
32-lead PLCC Top View
21 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
1160 32-plcc P01.0
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard Pinout Top View Die Up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1160 32-tsop P02.0
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM
(c)2004 Silicon Storage Technology, Inc.
X
14MM)
S71160-10-000 2/04
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4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet TABLE 2: PIN DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Pin Name Address Inputs Data Input/output Functions To provide memory addresses. During Sector-Erase AMS-A8 address lines will select the sector. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 4.5-5.5V for SST29SF040 2.7-3.6V for SST29VF040
CE# OE# WE# VDD VSS NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
Pin not connected internally
T2.4 1160
1. AMS = Most significant address AMS = A18 for SST29SF/VF040
TABLE 3: OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 4
T3.4 1160
CE# VIL VIL VIL VIH X X
OE# VIL VIH VIH X VIL X
WE# VIH VIL VIL X X VIH
DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT
Address AIN AIN Sector address, XXH for Chip-Erase X X X
1. X can be VIL or VIH, but no other value.
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4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Chip-Erase Software ID Entry4,5 Software ID Exit6 Software ID Exit6 1st Bus Write Cycle Addr1 555H 555H 555H 555H XXH 555H Data AAH AAH AAH AAH F0H AAH 2AAH 55H 555H F0H
T4.6 1160
2nd Bus Write Cycle Addr1 2AAH 2AAH 2AAH 2AAH Data 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 555H 555H 555H 555H Data A0H 80H 80H 90H
4th Bus Write Cycle Addr1 BA2 555H 555H Data Data AAH AAH
5th Bus Write Cycle Addr1 2AAH 2AAH Data 55H 55H
6th Bus Write Cycle Addr1 SAX3 555H Data 20H 10H
1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF040. AMS = Most significant address AMS = A18 for SST29SF/VF040. 2. BA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A7 address lines for SST29SF/VF040 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer's ID = BFH, is read with A0 = 0, SST29SF040 Device ID = 13H, is read with A0 = 1 SST29VF040 Device ID = 14H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent
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6
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Industrial
FOR
SST29SF040
VDD 4.5-5.5V 4.5-5.5V
OPERATING RANGE
Range Commercial Industrial
FOR
SST29VF040
VDD 2.7-3.6V 2.7-3.6V
Ambient Temp 0C to +70C -40C to +85C
Ambient Temp 0C to +70C -40C to +85C
AC CONDITIONS
OF
TEST
30 pF
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = See Figures 12, 13, and 14
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V FOR SST29SF040
Limits Symbol IDD Parameter Power Supply Current Read Program and Erase ISB1 ISB2 ILI ILO VIL VIH VIHC VOL VOH Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage 2.4 2.0 VDD-0.3 0.4 25 30 3 100 1 10 0.8 mA mA mA A A A V V V V V Min Max Units Test Conditions Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIH, VDD=VDD Max CE#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=2.1 mA, VDD=VDD Min IOH=-400 A, VDD=VDD Min
T5.6 1160
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S71160-10-000
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7
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet TABLE 6: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V FOR SST29VF040
Limits Symbol IDD Parameter Power Supply Current Read Program and Erase ISB ILI ILO VIL VIH VIHC VOL VOH Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 0.2 25 30 15 1 10 0.8 mA mA A A A V V V V V Min Max Units Test Conditions Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T6.8 1160
TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
1
Parameter Power-up to Read Operation Power-up to Program/Erase Operation
Minimum 100 100
Units s s
T7.1 1160
TPU-WRITE1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE (Ta = 25C, f=1 Mhz, other pins open)
Parameter CI/O
1
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T8.1 1160
CIN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T9.2 1160
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
AC CHARACTERISTICS
TABLE 10: READ CYCLE TIMING PARAMETERS VDD = 4.5-5.5V FOR SST29SF040 AND 2.7-3.6V
Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ TOH
1 1
FOR
SST29VF040
SST29VF040-70 Min 70 55 55 30 70 70 35 0 0 20 20 25 25 0 Max Units ns ns ns ns ns ns ns ns ns
T10.9 1160
SST29SF/VF040-55 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output
Output Hold from Address Change
Min 55
Max
0 0
TOHZ1
0
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD = 4.5-5.5V FOR SST29SF040 AND 2.7-3.6V
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH TDS TDH TSE TSCE
1 1
FOR
SST29VF040
Min 0 30 0 0 0 10 40 40 30 30 40 0 150 25 100 Max 20 Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
T11.8 1160
Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Chip-Erase
TIDA1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
TRC ADDRESS AMS-0
TAA
CE#
TCE
OE# VIH WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
1160 F03.0
DQ7-0
HIGH-Z
TCLZ
TOH DATA VALID
Note: AMS = Most Significant Address AMS = A18 for SST29SF/VF040
FIGURE 3: READ CYCLE TIMING DIAGRAM
Internal Program Operation Starts TBP ADDRESS AMS-0 555 TAH TWP WE# TAS OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TWPH TDS 2AA 555 ADDR TDH
1160 F04.0
Note: AMS = Most Significant Address AMS = A18 for SST29SF/VF040
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
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10
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
Internal Program Operation Starts TBP ADDRESS AMS-0 555 TAH TCP CE# TAS OE# TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TCPH TDS 2AA 555 ADDR TDH
1160 F05.0
Note: AMS = Most Significant Address AMS = A18 for SST29SF/VF040
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TCE CE# TOEH OE# TOE WE# TOES
DQ7
D
Note: AMS = Most Significant Address AMS = A18 for SST29SF/VF040
D#
D#
D
1160 F06.0
FIGURE 6: DATA# POLLING TIMING DIAGRAM
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11
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
ADDRESS AMS-0 TCE CE# TOEH OE# TOE TOES
WE#
DQ6
TWO READ CYCLES WITH SAME OUTPUTS 1160 F07.0
Note: AMS = Most Significant Address AMS = A18 for SST29SF/VF040
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
Six-Byte Code for Sector-Erase ADDRESS AMS-0 555 2AA 555 555 2AA SAX
TSE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
20 SW5
1160 F08.0
Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 11) AMS = Most significant address AMS = A18 for SST29SF/VF040
FIGURE 8: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
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12
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
Six-Byte Code for Chip-Erase ADDRESS AMS-0 555 2AA 555 555 2AA 555
TSCE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
1160 F09.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 11) Note: AMS = Most Significant Address AMS = A18 for SST29SF/VF040
FIGURE 9: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-Byte Sequence for Software ID Entry ADDRESS A14-0 555 2AA 555 0000 0001
CE#
TIDA
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2 TAA BF Device ID
1160 F10.0
Note: Device ID = 13H for SST29SF040 14H for SST29VF040
FIGURE 10: SOFTWARE ID ENTRY
AND
READ
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13
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
Three-Byte Sequence for Sofware ID Exit and Reset
ADDRESS A14-0
555
2AA
555
DQ7-0
AA
55
F0 TIDA
CE#
OE# TWP WE# TWHP
1160 F11.1
SW0
SW1
SW2
FIGURE 11: SOFTWARE ID EXIT AND RESET
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14
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1160 F12.0
AC test inputs are driven at VIHT (3.0 V) for a logic "1" and VILT (0 V) for a logic "0". Measurement reference points for inputs and outputs are VIT (1.5 V) and VOT (1.5 V). Input rise and fall times (10% 90%) are <10 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS
FOR
SST29SF040
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1160 F12.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
FOR
SST29VF040
SST29SF040
VDD TO TESTER RL HIGH TO DUT CL RL LOW
1160 F14a.0 1160 F14b.0
SST29VF040
TO TESTER TO DUT CL
FIGURE 14: TEST LOAD EXAMPLES
(c)2004 Silicon Storage Technology, Inc. S71160-10-000 2/04
15
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
Start
Load data: AAH Address: 555H
Load data: 55H Address: 2AAH
Load data: A0H Address: 555H
Load Byte Address/Byte Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
1160 F15.0
FIGURE 15: BYTE-PROGRAM ALGORITHM
(c)2004 Silicon Storage Technology, Inc.
S71160-10-000
2/04
16
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
Internal Timer ByteProgram/Erase Initiated
Toggle Bit ByteProgram/Erase Initiated
Data# Polling ByteProgram/Erase Initiated
Wait TBP, TSCE, or TSE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes
Program/Erase Completed
Program/Erase Completed
1160 F16.0
FIGURE 16: WAIT OPTIONS
(c)2004 Silicon Storage Technology, Inc.
S71160-10-000
2/04
17
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
Software ID Entry Command Sequence
Software ID Exit & Reset Command Sequence
Load data: AAH Address: 555H
Load data: AAH Address: 555H
Load data: F0H Address: XXH
Load data: 55H Address: 2AAH
Load data: 55H Address: 2AAH
Wait TIDA
Load data: 90H Address: 555H
Load data: F0H Address: 555H
Return to normal operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal operation
1160 F17.0
FIGURE 17: SOFTWARE ID COMMAND FLOWCHARTS
(c)2004 Silicon Storage Technology, Inc.
S71160-10-000
2/04
18
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
Chip-Erase Command Sequence Load data: AAH Address: 555H
Sector-Erase Command Sequence Load data: AAH Address: 555H
Load data: 55H Address: 2AAH
Load data: 55H Address: 2AAH
Load data: 80H Address: 555H
Load data: 80H Address: 555H
Load data: AAH Address: 555H
Load data: AAH Address: 555H
Load data: 55H Address: 2AAH
Load data: 55H Address: 2AAH
Load data: 10H Address: 555H
Load data: 20H Address: SAX
Wait TSCE
Wait TSE
Chip erased to FFH
Sector erased to FFH
1160 F18.0
FIGURE 18: ERASE COMMAND SEQUENCE
(c)2004 Silicon Storage Technology, Inc.
S71160-10-000
2/04
19
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
PRODUCT ORDERING INFORMATION
SST 29 XX VF 040 XX XXXX - 55 - XXX 4C XX NH - XXX E X Environmental Attribute E = non-Pb Package Modifier H = 32 pins or leads Package Type N = PLCC W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 55 = 55 ns 70 = 70 ns Device Density 040 = 4 Mbit Function F = Chip- or Sector-Erase Byte-Program Voltage S = 4.5-5.5V V = 2.7-3.6V Product Series 29 = Small-Sector Flash (128 Byte) Valid combinations for SST29SF040 SST29SF040-55-4C-NH SST29SF040-55-4C-NHE SST29SF040-55-4I-NH SST29SF040-55-4I-NHE SST29SF040-55-4C-WH SST29SF040-55-4C-WHE SST29SF040-55-4I-WH SST29SF040-55-4I-WHE
Valid combinations for SST29VF040 SST29VF040-55-4C-NH SST29VF040-55-4C-NHE SST29VF040-70-4C-NH SST29VF040-70-4C-NHE SST29VF040-55-4I-NH SST29VF040-55-4I-NHE SST29VF040-70-4I-NH SST29VF040-70-4I-NHE SST29VF040-55-4C-WH SST29VF040-55-4C-WHE SST29VF040-70-4C-WH SST29VF040-70-4C-WHE SST29VF040-55-4I-WH SST29VF040-55-4I-WHE SST29VF040-70-4I-WH SST29VF040-70-4I-WHE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2004 Silicon Storage Technology, Inc. S71160-10-000 2/04
20
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447
2 1 32
SIDE VIEW
.112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 BSC .490
.050 BSC .015 Min. .050 BSC .095 .075 .140 .125 .032 .026
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
1.05 0.95 0.50 BSC
Pin # 1 Identifier
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
32-tsop-WH-7
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH
(c)2004 Silicon Storage Technology, Inc.
X
14MM
S71160-10-000
2/04
21
4 Mbit Small-Sector Flash SST29SF040 / SST29VF040
Data Sheet
TABLE 12: REVISION HISTORY
Number 05 06 Description Date May 2002
* * * * * *
2002 Data Book
Mar 2003 Removed 512 Kbit, 1 Mbit, and 2 Mbit parts Commercial temperature and 70 ns parts removed PH package is no longer offered Part number changes - see page 20 for additional information Changes to Tables 5 and 6 on page 7 and page 8: - Clarified Test Conditions for Power Supply Current and Read parameters - Clarified IDD Write to be Program and Erase - Corrected IDD Program and Erase from 20 mA to 30 mA - Corrected IDD Read from 20 mA to 25 mA * Clarified measurement reference points VIT and VOT to be 1.5V instead of 1.5VDD * Corrected the VOL test condition IOL to be 2.1 mA instead of 2.1 A in Table 5 on page 7
07 08 09 10
* * * * *
Corrected the Test Conditions for the Read Parameter in Table 5 on page 7 Added Commercial temperatures for all packages (See page 20 for details) 2004 Data Book Changed status to "Data Sheet" Added 70 ns technical data and MPNs for SST29VF040 only
Apr 2003 Aug 2003 Dec 2003 Feb 2004
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2004 Silicon Storage Technology, Inc. S71160-10-000 2/04
22

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